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CXA2104S
US Audio Multiplexing Decoder
Description The CXA2104S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction. Various kinds of filters are built in while adjustment and mode control are all executed through I2C BUS. Features * Adjustment free of VCO and filter. * Audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. Almost any sort of signal processing is possible through this IC. * All adjustments are possible through I2C BUS to allow for automatic adjustment. * Various built-in filter circuits greatly reduce external parts. * There is an additional SAP output. Standard I/O Level * Input level COMPIN (Pin 11) 30 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC 11 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 1.35 Range of Operating Supply Voltage 9 0.5
V C C W
V
Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting 100mVrms 245mVrms (Selected by INSW) 490mVrms A license of the dbx-TV noise reduction system is required for the use of this device.
NOISETC SAPOUT VCATC VEOUT VEWGT SUBOUT
* Output level TVOUT-L/R (Pins 2 and 1) Pin Configuration (Top View)
VCAWGT
Structure Bipolar silicon monolithic IC
VCAIN
SAPIN
SOUT
VETC
STIN
NC
VE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MAINOUT
DGND
TVOUT-R
PCINT1
MAININ
PLINT
GND
SDA
VGR
TVOUT-L
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
COMPIN
PCINT2
SAPTC
SCL
IREF
VCC
E97726B96-PS
Block Diagram
PCINT2
SUBOUT
MAINOUT
PCINT1
PLINT
8 7
9 10 17
STLPF
LFLT MATRIX
VCO
1/4
1/2 2 1 TVOUT-L TVOUT-R
FLT
LPF
VCA
"STEREO" DeEm LPF NRSW/FOMO/SAPC (+6dB) WIDEBAND
COMPIN 11
VCA
LPF
ATT/INSW LOGIC
STIND
VCC 16
GND 14 LPF DeEm "NOISE" "SAP" HPF RMSDET VE VCA LPF 30 SOUT
BPF
SAPVCO
NOISETC 19
NOISE DET
SAPTC 15
SAPIND SPECTRAL AMP (+4dB) LPF LPF RMSDET
IREF "PONRES" 4 3 20 21
I2C BUS I/F SW
12
13
5
18
22
23
24
25
26
MAININ
6 28 27
SCL
VGR
IREF
SDA
STIN
VE
SAPIN
VETC
DGND
VCAIN
SAPOUT
VEWGT
VEOUT
VCAWGT
VCATC
-2-
CXA2104S
CXA2104S
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC 3k
(Ta = 25C, VCC = 9V) Description
1
TVOUT-R
4.0V
580 1 2 580
TVOUT right channel output pin.
2
TVOUT-L
4.0V
TVOUT left channel output pin.
VCC 7.5k 35 2.1V x2 4k x5
3
SDA
--
7.5k
4.5k
3k
Serial data I/O pin. VIH > 3.0V VIL < 1.5V
3
VCC 7.5k 35 2.1V 4k 10.5k x4 3k
4
SCL
--
Serial clock input pin. VIH > 3.0V VIL < 1.5V
4
5
DGND
--
5
Digital block GND.
VCC 10k
VCC
6
MAININ
4.0V
147 6 53k 4V
Input the (L + R) signal from MAINOUT (Pin 7).
-3-
CXA2104S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 15k x4 VCC
Description
7
MAINOUT
4.0V
147 7
(L + R) signal output pin.
200
1k
VCC 147 8
8
PCINT1
4.0V
30k
22k
VCC 147 9
Stereo block PLL loop filter integrating pin.
9
PCINT2
4.0V
2k
10k
10k
x2 4k
VCC 20k 20k
147
10
PLINT
5.1V
20k 20k
10
Pilot cancel circuit loop filter integrating pin. (Connect a 1F capacitor between this pin and GND.)
26
20k 50
10k
-4-
CXA2104S
Pin No.
Symbol
Pin voltage
24k
Equivalent circuit
VCC 24k
Description
14k
147 11
11
COMPIN
4.0V
34k 4V 24k
Audio multiplexing signal input pin.
3k
147
12
VGR
1.3V
11k
9.7k
19.4k x4
VCC 11k 11k
Band gap reference output pin. (Connect a 10F capacitor between this pin and GND.)
12
2.06k
VCC 40k 40k 30k 30k 15k x2 30k
VCC
13
IREF
1.3V
30p 1.8k 13 147 6.3k
Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62k (1%) resistor between this pin and GND.)
16k
14
GND
--
VCC 8k
14
Analog block GND.
10k 3k 1k VCC 4k 50 15
15
SAPTC
4.5V
Set the time constant for the SAP carrier detection circuit. (Connect a 4.7F capacitor between this pin and GND.)
-5-
CXA2104S
Pin No. 16
Symbol VCC
Pin voltage --
Equivalent circuit
16 Vcc 2k 2k 10P 4k
Description Supply voltage pin.
580
17
SUBOUT
4.0V
2k 2k 14.4k 580 147
17
(L-R) signal output pin.
2k
4k
1k
VCC
18
STIN
4.0V
23k
23k
Input the (L-R) signal from SUBOUT (Pin 17).
11.7k 147 18 147 21 18k 4V 20k 4V
Vcc 8k 3.3k
21
SAPIN
4.0V
18k
Input the (SAP) signal from SAPOUT (Pin 20).
10k 1k 2k 4k 4V 3k Vcc 3k
19
NOISETC
3.0V
x2
Set the time constant for the noise detection circuit. (Connect a 4.7F capacitor between this pin and GND.)
200k 19
-6-
CXA2104S
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc 5P
Description
580
20
SAPOUT
4.0V
580
10k 20 147
SAP FM detector output pin.
24k 10
4k 50
VCC 7.5k
22
VE
4.0V
147 22
Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3k resistor in series between this pin and GND.)
Vcc
580
2.9V 4V 36k
23
VEWGT
4.0V
23 147 580
Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047F capacitor and a 3k resistor in series between this pin and GND.)
8k
30k 8
4k 50
Vcc
24
VETC
1.7V
x4
x4
24
4k 50
20k 7.5
Determine the restoration time constant of the variable de-rmphasis control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 3.3F capacitor between this pin and GND.)
-7-
CXA2104S
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc 5P 580
Description
25
VEOUT
4.0V
25 580 10k
Variable de-emphasis output pin. (Connect a 4.7F non-polar capacitor between Pins 25 and 26.)
VCC
47k 20k
47k
26
VCAIN
4.0V
VCC
26
VCA input pin. Input the variable de-emphasis output signal from Pin 25 via a coupling capacitor.
VCC
x4
27 x4
27
VCATC
1.7V
50
4k
7.5
20k
Determine the restoration time constant of the VCA control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 10F capacitor between this pin and GND.)
VCC 40k 40k 3p
580
28
VCAWGT
4.0V
28 2.9V 36k 580 147
Weight the VCA control effective value detection circuit. (Connect a 1F capacitor and a 3.9k resistor in series between this pin and GND.)
50
4k 8
30k
8k
29
NC
--
29
--
-8-
CXA2104S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 15k x4
Description
30
SOUT
4.0V
30
Additional SAP output pin.
200
1k
-9-
Electrical Characteristics COMPIN input level (100% modulation level) INSW = 0 = 245mVrms = 100mVrms = 200mVrms = 20mVrms = 60mVrms (Ta = 25C, VCC = 9V)
Input pin Input signal Min. 22 1/2 20 log ('5k'/'1k') 1/2 1/2 15kLPF 15kLPF 20 log ('100%'/'0%') 15kLPF 1/2 1/2 1/2 17 20 log ('12k'/'1k') 15kLPF 15kLPF 20 log ('100%'/'0%')
SUB (L-R) 1kHz, NR OFF SUB (L-R) 1kHz, 100% mod., NR ON, SAP Carrier (5fH) No signal Mono 1kHz 100% mod. Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 12kHz 30% mod. 20 log Pre-em. ON ('12k'/'1k') Mono 1kHz 100% mod. Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz, Pre-em. ON SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF
INSW = 1
Main (L + R) (Pre-Emphasis: OFF) = 490mVrms = 49mVrms = 147mVrms
SUB (L - R) (dbx-TV: OFF)
Pilot
SAP Carrier
fH = 15.734kHz
No. -- MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP 11 11 11 11 11 11 11 11 11 11 11 11 440 -1.2 -3.0 - - 61 150 17 17 17 15kLPF 1kBPF 17 20 log ('NRSW = 0'/ 'NRSW = 1') 2 -3.0 - - 56 60
Item
Signal
Mode Filter
Measurement conditions Output pin
Typ. 32 490 0 -1.0 0.1 0.15 69 190 -0.5 0.1 0.2 64 70
Max. 42 540 1.0 1.0 0.5 0.5 - 230 1.0 1.0 2.0 - -
Unit mA mVrms dB dB % % dB mVrms dB % % dB dB
1
Current consumption
Icc
2
Main output level
Vmain
3
Main de-emphasis frequency characteristic
FCdeem
- 10 -
4
Main LPF frequency characteristic
FCmain
5
Main distortion
THDm
6
Main overload distortion
THDmmax
7
Main S/N
SNmain
8
Sub output level
Vsub
9
Sub LPF frequency characteristic
FCsub
10
Sub distortion
THDsub
11
Sub overload distortion
THDsmax
12
Sub S/N
SNsub
CXA2104S
13
ST SAP Crosstalk
CTst
No. ST
PILOT (fH) 0dB
Item 11 17 -9.0 BUS RETURN 2.0 150 -3.0 0 2.5 55 70 -12.0 BUS RETURN 2.0 15kLPF 15kLPF 15kLPF 15kLPF 1/2 1/2 1/2 1/2 23 23 23 23 -9.0 4.0 35 35 35 35 - 46 60 190 230 2.5 6.0 - - -6.5 6.0 - - - - 6.0 10.0 -6.0 -3.0 dB dB mVrms dB % dB dB dB dB dB dB dB dB dB 0dB = 49mVrms ST 20 log (`on level'/'off level') 20 20 15kLPF 20 log ('100%'/'0%') 15kLPF 1kBPF 2 20 20 11
Change PILOT (fH) Level
Signal Mode Input signal Min. Unit - -42 -30 Typ. Max. 0dB = 49mVrms fH BPF
Input pin
Measurement conditions Filter
Output pin
14
Sub pilot leak
PCsub
15
Stereo ON level
THst
16 SAP SAP SAP SAP ST 0dB = 147mVrms 20 log (`on level'/'off level') 11 SAP 1kHz 100% mod. 20 log ('NRSW = 1'/'NRSW = 0') NR ON, Pilot (fH) Change SAP Carrier (5fH) Level ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON 11 SAP 1kHz, NR OFF 11 SAP 1kHz 100% mod. NR OFF 11 SAP 10kHz 30% mod. 20 log ('10k'/'1k') NR OFF 11 SAP 1kHz 100% mod. NR OFF
Stereo ON/OFF hysteresis
HYst
17
SAP output level
Vsap
18
SAP LPF frequency characteristic
FCsap
19
SAP distortion
THDsap
20
SAP S/N
SNsap
21
SAP ST Cross talk SAP 11
CTsap
- 11 -
ST ST ST ST 11 11 11 11
22
SAP ON level
THsap
23
SAP ON/OFF hysteresis
HYsap
24
ST separation 1 L R
STLsep1
25
ST separation 1 R L
STRsep1
26
ST separation 2 L R
STLsep2
27
ST separation 2 R L
STRsep2
CXA2104S
Electrical Characteristics Measurement Circuit
BUFF FILTERS 15kHz LPF fH BPF 1kHz BPF MEASURES
S5 S4 S3 S2 S1
TANTALUM
C4 1 C9 C12 0.047 2700P 23 22 20 21 17 19 18 16 28 25 24 27 26
30
29
TANTALUM
C2 4.7 C5 10 C6 4.7 C8 3.3 C14 4.7 C18 4.7
R2 3.9k R5 3k C17 4.7 C20 100 R7 3.3k
VCC
NC
VE
SOUT
VETC
VCAIN
SAPIN
STIN
VCC
VCATC
VEOUT
VEWGT
SAPOUT
VCAWGT
NOISETC
SUBOUT
V2 9V GND
DGND
MAINOUT
PCINT2
COMPIN
SDA
TVOUT-R
MAININ
PCINT1
PLINT
VGR
GND
SCL
TVOUT-L
1 3 R1 220 C7 4.7 C10 5600p R3 220 R6 1MEG C13 1 4 7 8 10
2
5
6 9
11 C15 4.7
12 C16 10
13 R8 62k
IREF
14
15 C19 4.7 METAL 1% SIGNAL GENERATOR
C1 4.7
C3 4.7
I2C BUS DATA
DGND
R4 C11 100k 0.012
V1 AC
GND
GND
SAPTC
- 12 -
CXA2104S
CXA2104S
Adjustment Method (This is the case when standard input level is 245mVrms.) 1. ATT adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the "ATT" data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms). 3) Adjustment range: 30% Adjustment bits: 4 bits 2.Separation adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce TVOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the "SPECTRAL" adjustment data to reduce TVOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. 5) "WIDEBAND" "SPECTRAL" Adjustment range: 30% Adjustment range: 15% Adjustment bits: 6 bits Adjustment bits: 6 bits Adjust this IC through Tuner and IF when this IC is mounted in the set.
- 13 -
CXA2104S
Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV kHz 50 AM-DSB-SC 50
25
25
L-R dbx-TV NR
PILOT
15 SAP dbx-TV NR FM 10kHz 50 - 10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f
L+R 5 50 - 15kHz fH
fH = 15.734kHz
Fig. 1. Base band spectrum
I C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN)
2
PLL (VCO 8fH) STEREO LPF MVCA
2fHL0 fHL90 fHL0
PILOT DET
(COMPIN)
MAIN LPF DE.EM PILOT CANCEL SUB LPF L-R (DSB) DET
11
7
L+R WIDEBAND SUBVCA 4.7
6
(SUBOUT) (ST IN)
MATRIX (Lch) NR SW to TVSW
17
L - R 4.7
18
SAP BPF
SAP (FM) DET SAP LPF INJ. LOCK
A
(SAP OUT) (SAP IN)
dbx-TV BLOCK
B
(Rch)
20
4.7 NOISE DET I 2C BUS DECODER
21
LPF
(SOUT)
SAP DET
I 2C BUS DECODER MODE CONTROL
30
MODE CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN) FIXED VARIABLE DEEMPHASIS DEEMPHASIS (VE OUT)
18
(SAP IN)
NR SW
A
(VCA IN)
B
VCA to MATRIX
25
4.7 HPF LPF LPF RMS DET RMS DET
26
21
Fig 3. dbx-TV block - 14 -
CXA2104S
(1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L - R (SUB) The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 20 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5) dbx-TV block Either the L - R signal or SAP signal input respectively from ST IN (Pin 18) or SAP IN (Pin 21) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix The signals (L + R, L - R, SAP) input to "MATRIX" become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. (7) Others "MVCA" is a VCA which adjusts the input signal level to the standard level of this IC. "Bias" supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 13) with GND become the reference current.
- 15 -
CXA2104S
Register Specifications Slave address SLAVE RECEIVER 84H (1000 0100) Register table SUB ADDRESS MSB LSB BIT7 DATA1 INSW DATA2 DATA5 BIT6 BIT5 TEST-DA 0000 0001 0010 0011 0100 DATA BIT4 TEST1 BIT3 BIT2 BIT1 BIT0 SLAVE TRANSMITTER 85H (1000 0101)
ATT (4) SPECTRAL (6) WIDEBAND (6) NRSW ATTSW FOMO FST SAPC DATA3 M1 DATA4 : Don't Care
Status Registers STA1 BIT7 STA2 BIT6 STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 -- STA6 BIT2 -- STA7 BIT1 -- STA8 BIT0 --
POWER STEREO ON RESET
- 16 -
CXA2104S
Description of Registers Control registers Register ATT SPECTRAL WIDEBAND TEST-DA TEST1 FST NRSW FOMO M1 ATTSW INSW SAPC DATA1 DATA2 DATA3 DATA4 DATA5 Number of bits 4 6 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Classification1 A A A T T T U U U S S S T T T T T Standard setting 9 1F 1F 0 0 0 -- -- 1 -- -- -- 0 0 0 0 0 Test mode (Normal standard setting value) Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) Turn to DAC test mode by means of TEST-DA = 1. Turn to test mode by means of TEST = 1. Turn to forced stereo by means of FST = 1. Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO = 1. (Left channel only is MONO during SAP output.) Selection of TVOUT mute ON/OFF (0: mute ON, 1: mute OFF) Turn the input stage MVCA off when ATTSW = 1. Selection of standard input level Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Contents
1 Classification U: User control A: Adjustment S: Proper to set T: Test
Status registers Register PONRES STEREO SAP NOISE Number of bits 1 1 1 1 POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP signal; Contents 1: RESET 1: Stereo 1: SAP 1: Noise
- 17 -
CXA2104S
Description of Control Registers ATT (4): Adjust the signal level input to COMPIN (Pin 11) to the standard input level. Variable range of the input signal: standard input level -5.0dB to +3.0dB 0 = Level min. F = Level max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST-DA (1): Set DAC output test mode. 0 = Normal mode 1 = DAC output test mode In addition, the following output are present at Pin 2. TVOUT-L (Pin 2): DA control DC level TEST1 (1): Monitor SAPBPF and NRBPF output 0 = Normal mode 1 = SAPBPF, NRBPF output In addition, the following outputs are present at Pins 1 and 2. TVOUT-L (Pin 2): SAP BPF OUT TVOUT-R (Pin 1): NR BPF OUT Select forced STEREO mode 0 = Normal mode 1 = Forced stereo mode Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode
FST (1):
NRSW (1):
- 18 -
CXA2104S
FOMO (1):
Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Mute the TVOUT-L and TVOUT-R output. 0 = Mute ON 1 = Mute OFF Select BYPASS SW of MVCA 0 = Normal mode 1 = MVCA is passed Select standard input level of COMPIN (Pin 11). 0 = 245mVrms 1 = 100mVrms Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected
M1 (1):
ATTSW (1)
INSW (1):
SAPC (1):
- 19 -
CXA2104S
Description of Mode Control Mode control SAPC = 0 "Select dbx input and TV decoder output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) * During ST input: left channel: L, right channel: R * During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output) * When there is "SAP" during SAP discrimination - left channel: SAP, right channel: SAP * When there is "No SAP", output is the same as when NRSW = 0. SAPC = 1 "Select dbx input and TV decoder output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left
NRSW
NRSW = 1 (SAP output) * Regardless of the presence of SAP discrimination, dbx input: "SAP" left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (-7dB)
"Forced MONO" FOMO FOMO = 1 * During SAP output: left channel: L + R, right channel: SAP * During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for "MONO or ST output" and "SAP output". SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. "MUTE" M1 = 0: TVOUT output is muted.
SAPC
M1
- 20 -
CXA2104S
Decoder Output and Mode Control Table 1 (SAPC = 1) Input signal mode ST 0 0 MONO 1 0 0 0 0 1 1 1 STEREO 1 1 1 1 1 1 0 0 MONO & SAP 0 0 0 0 1 1 STEREO & SAP 1 1 1 1 Mode detection SAP 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode control NRSW 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 FOMO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch L+R SAP L+R L+R (SAP) L+R L L+R L L+R SAP L+R (SAP) L+R L+R L+R SAP L+R (SAP) L+R L L+R SAP L+R (SAP) L+R Rch L+R SAP SAP L+R (SAP) (SAP) R L+R R L+R SAP SAP (SAP) (SAP) L+R L+R SAP SAP (SAP) (SAP) R L+R SAP SAP (SAP) (SAP)
Note (SAP) : The SAPOUT output signal is soft muted (approximately -7dB). The signal is soft muted when NOISE = 1. : Don't care. 1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
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CXA2104S
Decoder Output and Mode Control Table 2 (SAPC = 0) Input signal mode ST 0 0 MONO 1 0 0 0 1 1 1 STEREO 1 1 1 1 1 1 0 0 0 MONO & SAP 0 0 0 0 0 1 1 1 STEREO & SAP 1 1 1 1 1 Mode detection SAP 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode control NRSW FOMO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L-R MUTE SAP SAP L-R MUTE (SAP) (SAP) Output Lch L+R L+R L+R (SAP) L+R L L+R L L+R L L+R (SAP) L+R L+R L+R SAP L+R L+R L+R (SAP) L+R L L+R SAP L+R L L+R (SAP) L+R Rch L+R L+R L+R (SAP) (SAP) R L+R R L+R R L+R (SAP) (SAP) L+R L+R SAP SAP L+R L+R (SAP) (SAP) R L+R SAP SAP R L+R (SAP) (SAP)
Note (SAP) : The SAPOUT output signal is soft muted (approximately -7dB). The signal is soft muted when NOISE = 1. : Don't care. 1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. - 22 -
CXA2104S
I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 3) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Item Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO Min. 3.0 0 -- -- 0 3 -- 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 10 10 0.4 -- 10 100 -- -- -- -- -- -- -- 1 300 -- ns s ns s s V A V mA pF kHz Unit
I2C BUS load conditions: Pull-up resistor 4k (Connect to +5V) Load capacity 200pF (Connect to GND)
I2C BUS Control Signal
SDA tBUF SCL P S tHD: STA tLOW tHIGH tSU: STA tSU: DAT Sr tSU: STO P tR tF tHD: STA
tHD: DAT
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CXA2104S
I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. * Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
* I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S Stop Condition P
SDA
SCL
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CXA2104S
* I2C data Write (Write from I2C controller to the IC)
L during Write MSB SDA HIZ MSB LSB HIZ
SCL S
1
2
3
4
5
6
7
8
9
1
8
9
Address MSB LSB HIZ HIZ
ACK
Sub Address
ACK
1
8
9
1
8
9
DATA (n)
ACK
DATA (n+1)
ACK
DATA (n + 2)
HIZ
HIZ
8
9
1
8
9 P
Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
DATA
ACK
DATA
ACK
* I2C data Read (Read from the IC to I2C controller)
H during Read HIZ SDA
SCL S
1
6
7
8
9
1
7
8
9 P
Address
ACK
DATA
ACK
* Read timing
MSB IC output SDA LSB
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
Data Read is performed during SCL rise.
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CXA2104S
Input level vs. Distortion characteristics 1 (MONO)
Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF Measurement point: TVOUT-L/R
Input level vs. Distortion characteristics 2 (Stereo)
Input signal: Stereo L = -R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, ST mode Measurement point: TVOUT-L/R
1.0
10
Distortion [%]
Distortion [%]
0.1 1.0 Standard level (100%) -10 0 Input level [dB] -10 0 Input level [dB] 10 Standard level (100%) 10
Input level vs. Distortion characteristics 3 (SAP)
Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, SAP mode Measurement point: TVOUT-L/R
10
Distortion [%]
1.0
Standard level (100%) -10 0 Input level [dB] 10
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CXA2104S
Stereo LPF frequency characteristics
10
Main LPF and Sub LPF frequency characteristics
30
5
Gain (FC main and FC sub) [dB]
20 10 0 -10 -20 -30 -40 -50
Gain [dB]
0
-5
-10
0
20
40
60
80
100
1
2
5
7
10
20
50 70 100
Frequency [kHz]
Frequency [kHz]
SAP frequency characteristics and group delay
100 20 5fH 10 Gain 90 80
Additional SAP frequency characteristics
500
Output level [mVrms]
Gain [dB]
60 0 50 40 -10 Group delay 3.8fH 20 40 60 80 30 20 -20 6.2fH 100 10 0 120
Group delay [s]
70
100% modulation
30% modulation
100
10% modulation
1% modulation
10 0.1
1.0 Frequency [kHz]
10
Frequency [kHz]
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CXA2104S
Package Outline
Unit: mm
30PIN SDIP (PLASTIC)
+ 0.4 26.9 - 0.1
30
16
+ 0.3 8.5 - 0.1
+ 0.1 .05 0.25 - 0
15 1.778
1
0.5 MIN
+ 0.4 3.7 - 0.1
10.16
0 to 15
Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type.
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-30P-01 SDIP030-P-0400 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 1.8g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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3.0 MIN

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